1. Field of the Invention
The present invention relates to a development system for a large scale integrated circuit for performing an application, and more specifically to a software/hardware partitioning program and method for determining the partition between software and hardware in developing a system-on-chip (SoC) for realizing the application.
2. Description of the Related Art
Recently, a system-on-chip (SoC) having a CPU and user hardware loaded on one chip has been widely used as an LSI for realizing an application, for example, the image processing in the H.264 system.
Generally, when the image processing is realized, there is the problem of outstanding arithmetic complexity for data, and it is efficient to allow hardware to process large amount of data, and the CPU to perform a controlling operation such as the management of processing time, etc. to enhance the processing speed. Thus, it is very important to improve the performance to appropriately determine the partition between hardware and software by determining which process is to be assigned to the hardware, and which process is to be the software.
That is, when one application is shared by a CPU and user hardware, the CPU performs a part of the application as a program while the user hardware has a part of software mounted as a hardware engine, thereby performing the application by the cooperation of the CPU and the user hardware. The design for partitioning an application between a CPU and hardware depends on the application and the architecture of the CPU.
Conventionally, to determine the partition between software and hardware, an operator manually partitions the source code of an application program between a portion to be processed by software and a portion to be processed by hardware, performs calculation on executable data by a visual C program using, for example, a computer, and evaluates the partition between software and hardware (SW/HW). However, there has been the problem with the method that the SW/HW partition cannot be appropriately evaluated between a built-in CPU practically loaded into the SoC and a user hardware.
The patent document 1 as a conventional technology relating to the simulation of a system description, the cooperative design between software and hardware, etc. discloses a method for simulating a description of a system specification capable of correcting measuring the runtime of candidates for software and hardware.
The patent document 2 discloses the technique of evaluating the capability of the software by determining the estimated value of the runtime of software based on a set of benchmark program and evaluating a model developed from the benchmark program.
The patent document 3 discloses a technology of integrating a simulation of hardware with a simulation of software into one application in such a way that each of them can be debugged, thereby realizing a high-speed cooperative simulation.
However, the above-mentioned conventional technology cannot solve the problem that the SW/HW partition between a built-in CPU and user hardware cannot be appropriate evaluated.
[Patent Document 1] Japanese Published Patent Application No. H11-259552 “Method For Simulating A Description Of System Specification”
[Patent Document 2] National Publication of International patent Application No. 2004-530193 “Method And Apparatus For Statistical Evaluation Of Runtime Of Built-In Software”
[Patent Document 3] Japanese Published Patent Application No. 2005-332110 “Simulation System”